The heart of the Deluxe RS-232 Pak is the Synertek 6551 ACIA.
It has an on-chip baud rate generator, programmable interrupts
and status register for ease of operation, false start bit
detection, and echo mode.
This ACIA board is memory mapped to addresses $FF68 to $FF6B.
The 6551 uses 4 memory addresses for the following functions:
$FF68 |
Transmit data Register |
Received data Register |
$FF69 |
Soft Reset |
Status Register |
$FF6A | Command Register |
$FF6B |
Control Register |
This table shows that only the Command and Control registers are bidirectional.
The Soft Reset operation clears the 6551 internal registers but does not cause
any data transfer. Therefore, the data written is a "don't care." A RES* from
the bus will clear all registers in the 6551 while a Soft Reset will disable
interrupts and transmitter, turn off echo mode, and clear the Overrun Error
flag only.
The following shows the Status, Command, and Control Register and gives
programming examples for each:
$FF69: Status Register
The Status Register is used to indicate to the processor the status of various
SY6551 functions.
STATUS | SET BY | CLEARED BY |
Parity Error* | 0 = No Error 1 = Error | Self Clearing** |
Framing Error* | 0 = No Error 1 = Error | Self Clearing** |
Overrun* | 0 = No Error 1 = Error | Self Clearing** |
Receive Data Register Full | 0 = Not Full 1 = Full | Read Receive Data Register |
Transmit Data Register Empty | 0 = Not Empty 1 = Empty | Write Transmit Data Register |
DCD | 0 = DCD Low 1 = DCD High | Net Reusable Reflects DSR State |
DSR | 0 = DSR Low 1 = DSR High | Net Reusable Reflects DSR State |
IRQ | 0 = No Interrupt 1 = Interrupt | Read Status Register |
*No interrupt generated for these conditions.
**Cleared automatically after a read of rdr and the next error free receipt of data.
HARDWARE RESET |
0 |
- |
- |
1 |
0 |
0 |
0 |
0 |
PROGRAM RESET |
- |
- |
- |
- |
- |
0 |
- |
- |
$FF6A: Command Register
The Command Register is used to control Specific Transmit/Receive functions.
7 |
6 |
5 |
- |
- |
0 |
Parity Disabled - No Parity Bit Generated - No Parity Bit Received |
0 |
0 |
1 |
Odd Parity Receiver and Transmitter |
0 |
1 |
1 |
Even Parity Receiver and Transmitter |
1 |
0 |
1 |
Mark Parity Bit Transmitted, Parity Check Disabled |
1 |
1 |
1 |
Space Parity Bit Transmitted, Parity Check Disabled |
0 |
Normal |
1 |
Echo (Bits 2 and 3 must be "0") |
3 |
2 |
0 |
0 |
Disabled |
High |
Off |
0 |
1 |
Enabled |
Low
| On |
1 |
0 |
Disabled |
Low |
On |
1 |
1 |
Disabled |
Low |
Transmit BRK |
0 |
IRQ Interrupt Enabled from Bit 3 of Status Register |
1 |
IRQ Interrupt Disabled |
0 |
Disable Receiver and All Interrupts (DTR high) |
1 |
Enable Receiver and All Interrupts (DTR low) |
HARDWARE RESET |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PROGRAM RESET |
- |
- |
- |
0 |
0 |
0 |
0 |
0 |
$FF6B: Control Register
The Control Register is used to select the desired mode for the
SY6551. The word length, number of stop bits, and clock controls
are all determined by the Control Register.
0 |
1 Stop Bit |
1 |
2 Stop Bits
1 Stop Bit if Word Length = 8 Bits and Parity*
1.5 Stop Bits if Word Length = 5 Bits and No Parity
|
*This allows for 9-bit transmission (8 data bits plus parity).
6 |
5 |
0 |
0 |
8 |
0 |
1 |
7 |
1 |
0 |
6 |
1 |
1 |
5 |
0 |
External Receiver Clock |
1 |
Baud Rate Generator |
3 |
2 |
1 |
0 |
0 |
0 |
0 |
0 |
16x ENTERNAL CLOCK* |
0 |
0 |
0 |
1 |
50 BAUD |
0 |
0 |
1 |
0 |
75 BAUD |
0 |
0 |
1 |
1 |
109.92 BAUD |
0 |
1 |
0 |
0 |
134.58 BAUD |
0 |
1 |
0 |
1 |
150 BAUD |
0 |
1 |
1 |
0 |
300 BAUD |
0 |
1 |
1 |
1 |
600 BAUD |
1 |
0 |
0 |
0 |
1200 BAUD |
1 |
0 |
0 |
1 |
1800 BAUD |
1 |
0 |
1 |
0 |
2400 BAUD |
1 |
0 |
1 |
1 |
3600 BAUD |
1 |
1 |
0 |
0 |
4800 BAUD |
1 |
1 |
0 |
1 |
7200 BAUD |
1 |
1 |
1 |
0 |
9600 BAUD |
1 |
1 |
1 |
1 |
19200 BAUD |
*This works out to be 115200 baud, and it *almost* works!
HARDWARE RESET |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
PROGRAM RESET |
- |
- |
- |
- |
- |
- |
- |
- |
RS-232C Pin Description
1 |
Frame Ground |
2 |
Transmit Data |
3 |
Receive Data |
4 |
Request to Send |
5 |
Clear to Send |
6 |
Data Set Ready |
7 |
Signal Ground |
8 |
Carrier Detect |
20 |
Data Terminal Ready |
|