$FF90 - INIT0 : Initialization Register 0 | ||
Bit 7 | COCO | 1=CoCo 1/2 compatible mode |
Bit 6 | MMUEN | 1=MMU enabled |
Bit 5 | IEN | 1=GIME chip IRQ enabled |
Bit 4 | FEN | 1=GIME chip FIRQ enabled |
Bit 3 | MC3 | 1=RAM at FExx is constant (secondary IRQ vectors) |
Bit 2 | MC2 | 1=standard SCS (spare chip select) |
Bit 1 | MC1 | ROM Map Control register 1 |
Bit 0 | MC0 | ROM Map Control register 0 |
COCO: This bit is used to toggle the CoCo compatible mode on and off. The
term CoCo compatible mode is somewhat of a misnomer as there are some CoCo 2
graphics modes, which are not supported by the CoCo 3, and some of the video
control registers are active even when the COCO bit is in the CoCo compatible mode.
The programmer is best advised to use this bit for exactly what it was intended for
- to be set when you are using CoCo 2 graphics modes and to be clear when you are
using the new CoCo 3 graphics modes. The descriptions of the CoCo 3 registers given
below will explicitly state those instances in which the programmer should use the
new registers with the COCO bit set. To use CoCo 3 graphics, the COCO bit must be set to zero. When using CoCo 1/2 rdesolutions, the bit is set to 1. RSDOS typically sets the INIT0 register to 196 in CoCo 2 resolutions and 68 when using CoCo 3 graphics modes. MMUEN : When this bit is set the MMU registers are enabled. If this bit is clear, the MMU registers are inoperable and the 64K, which makes up the logical address space is, the contiguous segment from $70000 - $7FFFF. IEN : When this bit is set, the GIME chip’s IRQ Interrupt structure is enabled. If the bit is clear, the old CoCo 2 PIA IRQ interrupt structure is used. FEN : When this bit is set, the GIME chip’s FIRQ Interrupt structure is enabled. If the bit is clear, the old CoCo 2 PIA FIRQ interrupt structure is used. MC3 : When this bit is set, the RAM which occupies the CPU’s address range of $FE00-$FEFF will always be taken from $7FE00-$.7FEFF. If this bit is clear and the MMUEN bit is set the RAM in the CPU’s address range of $FE00-$FEFF will be taken from the block as specified by the MMU register controlling logical block 7. MC2 : Spare Chip Select (SCS) control; if 0, then the SCS line (to the expansion slot) will only be active in the $FF50-$FF5F range. If this bit is 1, then the SCS line will be active in the $FF40-$FF5F range. MC1 : ROM map control MC0 : ROM map control MC1 and MC0 ROM configuration |