APPENDIX B
Sound Generator Registers
Operation
Since all functions of the PSG (Programmable Sound Generator) are controlled
by the processor via a series of register loads, a detailed description of
the PSG operation can best be accomplished by relating each PSG function to
the control of its corresponding register. The function of creating or
programming a specific sound or sound effect logically follows the control
sequence listed:
Operation Registers Function
Tone Generator Control R0--R5 Program tone periods.
Noise Generator Control R6 Program noise period.
Mixer Control R7 Enable tone and/ or noise on selected channels.
Amplitude Control R8--R10 Select "fixed" or "envelope-variable" amplitudes
Envelope Generator R11--R13 Program envelope Control period and select envelope pattern.
Tone Generator Control (Registers R0, Rl, R2, R3, R4, R5)
The frequency of each square wave generated by the three Tone Generators (one
each for Channels A, B, and C) is obtained in the PSG by first counting down
the input clock by 16, then by further counting down the result by the programmed
12-bit Tone Period value. Each 12-bit value is obtained in the PSG by combining
the contents of the relative Coarse and Fine Tune registers, as illustrated in
the following:
Coarse Tune Register Channel Fine Tune Register
R1 A R0
R3 B R2
R5 C R4
<graphic>
Noise Generator Control (Register R6)
The frequency of the noise source is obtained in the PSG by first counting down the input clock by 16 and then by further counting down the result by the programmed 5-bit Noise Period value. This 5-bit value consists of the lower 5 bits (B4--B0) of register R6, as illustrated in the following:
<Graphic>
Mixer Control (Register R7)
Register R7 is a multifunction Enable register that controls the three Noise/Tone Mixers.
The Mixers, as previously described, combine the noise and tone frequencies for each of the three channels. The determination of combining neither/either/both noise and tone frequencies on each channel is made by the state of bits B5--B0 of R7. These bits are active low.
These functions are illustrated in the following:
<Graphic>
Amplitude Control (Registers R8, R9, R10)
The amplitudes of the signals generated by each of the three D/A Converters (one each for Channels A, B, and 0 is determined by the contents of the lower 5 bits (B4--B0) of registers R8, R9, and Rlg as illustrated in the following:
<Graphic>
If Bit 4 is high, the envelope controls the amplitude; if Bit 4 is low, Bits 3-0 fix the amplitude.
Envelope Generator Control (Registers Rll, Rl2, Rl3)
To accomplish the generation of fairly complex envelope patterns, two independent methods of control are provided in the PSG. First, it is possible to vary the frequency of the envelope using registers Rll and R12. Second, the relative shape and cycle pattern of the envelope can be varied using register R13. The following paragraphs explain the details of the envelope control functions, describing first the envelope period control and then the envelope shape/cycle control.
ENVELOPE PERIOD CONTROL (Registers Rll, Rl2)
The frequency of the envelope is obtained in the PSG by first counting down the input clock by 256 and then by further counting down the result by the programmed 16-bit Envelope Period value. This 16-bit value is obtained in the PSG by combining the contents of the Envelope Coarse and Fine Tune registers, as illustrated in the following:
<graphic>
ENVELOPE SHAPE/CYCLE CONTROL (Register Rl3)
The Envelope Generator further counts down the envelope frequency by 16, producing a 16-state per cycle envelope pattern as defined by its 4-bit counter output, E3 E2 El E0, The particular shape and cycle pattern of any desired envelope is accomplished by controlling the count pattern (count up/count down) of the 4-bit counter and by defining a single-cycle or repeat-cycle pattern.
This envelope shape/cycle control is contained in the lower 4 bits (B3--Bfl) of register R13. Each of these 4 bits controls a function in the envelope generator as illustrated in the following:
<graphic>
Note: In determining the period of events, consider a count of zero as one more than if all bits are set. For example, in a tone, if 12 bits are set, the divisor is 4095. If all 12 bits are clear, however, the divisor is not 0 because division by zero is not permitted. Therefore, the divisor becomes 4096.
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