GIME Register Reference
From Super Extended Basic Unravelled



$FF90 - INIT0 : Initialization Register 0
Bit 7COCO1=CoCo 1/2 compatible mode
Bit 6MMUEN1=MMU enabled
Bit 5IEN1=GIME chip IRQ enabled
Bit 4FEN1=GIME chip FIRQ enabled
Bit 3MC31=RAM at FExx is constant (secondary IRQ vectors)
Bit 2MC21=standard SCS (spare chip select)
Bit 1MC1ROM Map Control register 1
Bit 0MC0ROM Map Control register 0

COCO: This bit is used to toggle the CoCo compatible mode on and off. The term CoCo compatible mode is somewhat of a misnomer as there are some CoCo 2 graphics modes, which are not supported by the CoCo 3, and some of the video control registers are active even when the COCO bit is in the CoCo compatible mode. The programmer is best advised to use this bit for exactly what it was intended for - to be set when you are using CoCo 2 graphics modes and to be clear when you are using the new CoCo 3 graphics modes. The descriptions of the CoCo 3 registers given below will explicitly state those instances in which the programmer should use the new registers with the COCO bit set.

To use CoCo 3 graphics, the COCO bit must be set to zero. When using CoCo 1/2 rdesolutions, the bit is set to 1. RSDOS typically sets the INIT0 register to 196 in CoCo 2 resolutions and 68 when using CoCo 3 graphics modes.


MMUEN : When this bit is set the MMU registers are enabled. If this bit is clear, the MMU registers are inoperable and the 64K, which makes up the logical address space is, the contiguous segment from $70000 - $7FFFF.


IEN : When this bit is set, the GIME chip’s IRQ Interrupt structure is enabled. If the bit is clear, the old CoCo 2 PIA IRQ interrupt structure is used.


FEN : When this bit is set, the GIME chip’s FIRQ Interrupt structure is enabled. If the bit is clear, the old CoCo 2 PIA FIRQ interrupt structure is used.


MC3 : When this bit is set, the RAM which occupies the CPU’s address range of $FE00-$FEFF will always be taken from $7FE00-$.7FEFF. If this bit is clear and the MMUEN bit is set the RAM in the CPU’s address range of $FE00-$FEFF will be taken from the block as specified by the MMU register controlling logical block 7.


MC2 : Spare Chip Select (SCS) control; if 0, then the SCS line (to the expansion slot) will only be active in the $FF50-$FF5F range. If this bit is 1, then the SCS line will be active in the $FF40-$FF5F range.


MC1 : ROM map control
MC0 : ROM map control
	MC1 and MC0 ROM configuration
0 X 16K internal, 16K external 1 0 32K internal 1 1 32K external (except interrupt vectors)



$FF91 - INIT1 : Initialization Register 1
Bit 7Unused
Bit 6?Memory type: 1 = 256K, 0 = 64K chips
Bit 5TINS Timer clock source: 1 = 279.365 nsec, 0 = 63.695 use
Bit 4Unused
Bit 2Unused
Bit 3Unused
Bit 1Unused
Bit 0 TR MMU task select
1 = enable FFA8-FFAF MMU registers
0 = enable FFA0-FFA7 MMU registers

TINS: This bit controls the clock input to the 12-bit interval timer. If the bit is set, the input source will be 14.31818 MHz which will produce a clock pulse approximately every 70 nanoseconds. If the bit is clear, the input source will be the horizontal blanking pulse which will produce a clock pulse approximately every 63.5 microseconds. The 279 ns clock is useful for interrupt driven sound routines while the 63 us clock is used for a slower timer.

TR (Task Register): The task register selects which set of MMU bank registers to assign to the CPU's 64K workspace. If this bit is set, then $FFA8-$FFAF will be the active MMU registers, if the bit is clear, then $FFA0-$FFA7 will be the active MMU registers. The task bit is generally set to zero in DECB.



$FF92 - IRQENR : Interrupt request enable register
Bit 7Unused
Bit 6Unused
Bit 5TMR1 = Enable timer IRQ
Bit 4HBORD1 = Enable Horizontal border IRQ
Bit 3VBORD1 = Enable Vertical border IRQ
Bit 2EI21 = Enable Serial data IRQ
Bit 1EI11 = Enable Keyboard IRQ
Bit 0EI01 = Enable Cartridge IRQ

TMR: A timer interrupt is generated whenever the 12-bit interval timer ($FF94-$FF95) counts down to zero.

HBORD: The horizontal border interrupt is generated on the falling edge of the horizontal sync pulse.

VBORD: The vertical border interrupt is generated on the falling edge of the vertical sync pulse.

EI2: The serial data interrupt is generated on the falling edge of a signal on pin 4 of the serial I/O connector (JK 3).

EI1: The keyboard interrupt will be triggered whenever a zero appears on any one of the PA0-PA6 pins of PIA0. These pins are normally programmed as inputs and are used to read the keyboard. The programmer should be warned that it is not chiseled into tablets of granite that these pins remain inputs - some interesting effects may be had by programming one as an output and using it to generate an interrupt. In their normal condition as inputs, an interrupt will be generated if a key is pressed and the proper keyboard column is strobed by placing a zero in the correct column strobe register ($FF00) bit OR if a joystick fire button is pressed. It is Important to note that a keyboard interrupt cannot be generated if there is not at least one zero in the keyboard column strobe register (ignoring joystick fire buttons). Also note that there is no way to mask off the joystick fire buttons - they will always generate a keyboard interrupt.

EI0: A cartridge interrupt will be generated on the falling edge of a Signal found on pin 8 (CART) of the expansion connector.

Reading from the register tells you which interrupts came in and acknowledges and resets the interrupt source.



$FF93 - FIRQENR : Fast Interrupt request enable register
Bit 7Unused
Bit 6Unused
Bit 5TMR 1 = Enable timer FIRQ
Bit 4HBORD1 = Enable Horizontal border FIRQ
Bit 3VBORD1 = Enable Vertical border FIRQ
Bit 2EI21 = Enable Serial data FIRQ
Bit 1EI11 = Enable Keyboard FIRQ
Bit 0EI01 = Enable Cartridge FIRQ

This register works the same as IRQENR except that it generates FIRQ interrupts.

Here's a table of the interrupt vectors and where they end up going. You can't change the $FFxx vectors, but you can change the $FExx and $01xx vectors which contain jmps/lbras to the interrupt routine.

Interrupt Hardware
Vector
CoCo III points to which jumps to
this routine
SWI3$FFF2$FEEE$0100
SWI2$FFF4$FEF1$0103
FIRQ$FFF6$FEF4$010F
IRQ$FFF8$FEF7$010C
SWI$FFFA$FEFA$0106
NMI$FFFC$FEFD$0109
RESET$FFFE$8C1B



$FF94 - TIMRMSB : Timer register MSB
Bit 7Unused
Bit 6Unused
Bit 5Unused
Bit 4Unused
Bit 3
Bit 2
Bit 1
Bit 0
TMRH Timer bits 8-11
$FF95 - TIMRLSB : Timer register LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMRL Timer bits 0-7

The 12 bit timer can be loaded with any number from 0-4095. The timer resets and restarts counting down as soon as a number is written to FF94. Writing to FF95 does not restart the timer, but the value does save. Reading from either register does not restart the timer. When the timer reaches zero, it automatically restarts and triggers an interrupt (if enabled). The timer also controls the rate of blinking text.

Storing a zero to both registers stops the timer from operating. Lastly, the timer works slightly differently on both 1986 and 1987 versions of the GIME. Neither can actually run a clock count of 1. That is, if you store a 1 into the timer register, the 1986 GIME actually processes this as a '3' and the 1987 GIME processes it as a '2'. All other values stored are affected the same way:

   nnn+2 for 1986 GIME
   nnn+1 for 1987 GIME



$FF98 - VMODE : Video mode register
Bit 7BP1=Graphics modes
0=Text modes
Bit 6Unused
Bit 5BPI1=Composite color phase invert
Bit 4MOCH1=Monochrome on Composite video out
Bit 3H501=50Hz video
0=60Hz video
Bits 2-0 LPR 00x = one line per row
010 = two lines per row
011 = eight lines per row
100 = nine lines per row
101 = ten lines per row
110 = eleven lines per row
111 = *infinite lines per row

BP (Bit Plane): Determines whether the computer is to display graphics or text. If this bit is set to 0, the screen is displayed as text. If it is 1, graphics are displayed.

BPI: Setting this bit will put you in the alternate color set. Technically, this bit tells the computer to invert the color burst phase going to the TV or composite monitor. Setting this bit will reverse the red and blue colors in the artifacting mode.

MOCH: When this bit is set to 1, the composite (including TV) output of the Color Computer 3 is changed to black and white (monochrome). This allows easier reading and better resolution in higher resolution text and graphics modes. This bit will not affect the RGB display.

H50: If this bit is set, the power source is 50 Hertz, if the bit is clear; the power source is 60 Hz.

LPR (Lines Per character Row): These bits determine the number of vertical lines used for each character in the text display. The one, two and three lines per row settings have little practical value, as the character itself is seven rows high. Changing the setting will not change the size of the character; it will only change the number of rows between characters. These settings only affect the way text is displayed on the screen; it has no effect on the amount of memory used to contain the screen data.

*Mostly useless, but it does generate a graphics mode where the whole screen is filled with the same line of graphics - like a 320x1 resolution. This can be used for a very fast oscilloscope type display where the program only updates data in one scan line over time and as the screen refreshes, you get a screen full of samples. I also used it in my Boink bouncing ball demo to take manual control of the vertical resolution of the screen to make the ball appear that it's going up and down (without actually scrolling the whole screen up and down).



$FF99 - VRES : Video resolution register
Bit 7Unused?
Bits 6-5 LPF 00 = 192 scan lines on screen
01 = 200 scan lines on screen
10 = *zero/infinite lines on screen (undefined)
11 = 225 scan lines on screen
Bits 4-2 HRES Horizontal resolution using graphics:
000 = 16 bytes per row
001 = 20 bytes per row
010 = 32 bytes per row
011 = 40 bytes per row
100 = 64 bytes per row
101 = 80 bytes per row
110 = 128 bytes per row
111 = 160 bytes per row

When using text:
0x0 = 32 characters per row
0x1 = 40 characters per row
1x0 = 64 characters per row
1x1 = 80 characters per row
Bits 1-0 CRES Color Resolution using graphics:
00 = 2 colors (8 pixels per byte)
01 = 4 colors (4 pixels per byte)
10 = 16 colors (2 pixels per byte)
11 = Undefined (would have been 256 colors)

When using text:
x0 =No color attributes
x1 =Color attributes enabled

*The zero/infinite scanlines setting will either set the screen to display nothing but border (zero lines) or graphics going all the way up and down out of the screen, never retriggering. It all depends on when you set the register. If you set it while the video raster was drawing the vertical border you get zero lines, and if you set it while video was drawing graphics you get infinite lines. Mostly useless, but it should be possible to coax a vertical overscan mode using this with some tricky timing.

HRESCRESCommonly used graphics modes
11101640 pixels, 4 colors
10100640 pixels, 2 colors
11001512 pixels, 4 colors
10000512 pixels, 2 colors
11110320 pixels, 16 colors
10101320 pixels, 4 colors
01100320 pixels, 2 colors
11010256 pixels, 16 colors
10001256 pixels, 4 colors
01000256 pixels, 2 colors
10110160 pixels, 16 colors
01101160 pixels, 4 colors
00100160 pixels, 2 colors
10010128 pixels, 16 colors
01001128 pixels, 4 colors
00000128 pixels, 2 colors



$FF9A - BRDR : Border color register
Bit 7Unused
Bit 6Unused
Bits 5-0BRDRBorder color

This controls the color of the border around the screen. The color bits work the same as the palette registers. This register only controls the border color of CoCo 3 video modes and does not affect Coco 1/2 modes.



$FF9B - Reserved
Bit 7Unused
Bit 6Unused
Bit 5Unused
Bit 4Unused
Bit 3Unused
Bit 2Unused
Bits 1-0 VBANK Used by Disto 2 Meg upgrades to switch video between 512K banks



$FF9C - VSC : Vertical scroll register
Bit 7Unused
Bit 6Unused
Bit 5Unused
Bit 4Unused
Bits 3-0VSCVertical smooth scroll.

The vertical scroll register is used to allow smooth scrolling in text modes. Consecutive numbers scroll the screen upwards one scan line at a time in video modes where more than one scan line makes up a row of text (typically 8 lines per character row) or graphics (double height+ graphics).



$FF9D - VORMSB : Vertical offset register MSB
Bits 7-0Y15-Y8MSB Start of video in RAM (video location * 2048)




$FF9E - VORLSB : Vertical offset register LSB
Bits 7-0Y7-Y0LSB Start of video in RAM
(video location * 8)

Y15-Y0 is used to set the video mode to start in any memory location in 512K by steps of 8 bytes. On a 128K machine, the memory range is $60000-$7FFFF. There is a bug in some versions of the GIME that causes the computer to crash when you set odd numbered values in $FF9E in some resolutions, so it's safest to limit positioning to steps of 16 bytes. Fortunately, you can use FF9F to make up for it and get steps as small as 2 bytes.




$FF9F - HOR : Horizontal Offset Register
Bit 7 HVEN 1 = Horizontal virtual screen enable (256 bytes per row)
0 = Normal horizontal display
Bits 6-0 X6-X0 Horizontal offset address
(video location * 2)

You can combine the horintal and vertical offsets to get a higher definition video position: Y15-Y4,X6-X0 which gives you 19 bit positioning by steps of 2 bytes.
Otherwise, you can use this register to do scrolling effects. The virtual screen mode allows you to set up a 256 byte wide graphics or text screen, showing only part of it at a time and allowing you to scroll it vertically.



$FFA0 - $FFA7 : MMU Registers [task 0]
$FFA0Bank at $0000-$1FFF
$FFA1Bank at $2000-$3FFF
$FFA2Bank at $4000-$5FFF
$FFA3Bank at $6000-$7FFF
$FFA4Bank at $8000-$9FFF
$FFA5Bank at $A000-$BFFF
$FFA6Bank at $C000-$DFFF
$FFA7Bank at $E000-$FFFF (or $E000-$FDFF if secondary vectors are enabled)
$FFA8 - $FFAF : MMU Registers [task 1]
$FFA8Bank at $0000-$1FFF
$FFA9Bank at $2000-$3FFF
$FFAABank at $4000-$5FFF
$FFABBank at $6000-$7FFF
$FFACBank at $8000-$9FFF
$FFADBank at $A000-$BFFF
$FFAEBank at $C000-$DFFF
$FFAFBank at $E000-$FFFF
(or $E000-$FDFF if secondary vectors enabled)

These MMU registers allocate chunks of 8K into the CPU's 64K address space. Valid bank ranges are $38-$3F on 128K machines, $00-$3F on a 512K machine, $00-$7F on a 1 Meg machine and $00-$FF on a 2 Meg machine.

These registers can be read, but the upper 2 bits must be masked out as they return bleedover from the bus (sometimes zero, sometimes one). This is okay for machines with 512K or less, but poses a problem for 1Meg and up. Supposedly some memory upgrades fixed this, but most don't so you can't rely on those 2 bits to be there when you read the registers.

The "Task 0" MMU registers are enabled when the task bit (FF91) is clear.
The "Task 1" MMU registers are enabled when the task bit (FF91) is set.



$FFB0 - $FFBF : Color palette registers
$FFB0Color 0
$FFB1Color 1
$FFB2Color 2
$FFB3Color 3
$FFB4Color 4
$FFB5Color 5
$FFB6Color 6
$FFB7Color 7
$FFB8Color 8
$FFB9Color 9
$FFBAColor 10
$FFBBColor 11
$FFBCColor 12
$FFBDColor 13
$FFBEColor 14
$FFBFColor 15
RGB Color format
Bit 7Unused
Bit 6Unused
Bit 5High order Red
Bit 4High order Green
Bit 3High order Blue
Bit 2Low order Red
Bit 1Low order Green
Bit 0Low order Blue
Composite Color format
Bit 7Unused
Bit 6Unused
Bits 5-4Intensity
Bits 3-0Coloe Hue

The color set when using composite monitors is different than above (which applies to RGB monitors). On composite displays, Bits 5-4 control 4 levels of intensity, and bits 3-0 control 16 hues of color.

These registers can also be read to determine what palettes are set but like the MMU registers, the upper 2 bits must be masked out. Both reading and writing to the palette registers causes a small 'glitch' on the screen. If you want to avoid them, you can change the palettes while the video is in the vertical or horizontal border.

On the other hand, you could also generate the glitches on purpose, to superimpose snow on the screen. The glitches appear as the color you set the register to (with a bit of the previous color setting at the beginning) and with precise CPU timing loops you could actually superimpose definable graphics over the screen this way.



$FFD8 and $FFD9 : CPU Clock Rate
FFD8'Slow poke'Any write selects 0.89 Mhz CPU clock
FFD9'Fast poke'Any write selects 1.79 Mhz CPU clock



$FFDE and $FFDF : ROM/RAM map type
FFDEROM modeAny write switches system ROMs into memory map
FFDFRAM modeAny write selects all-RAM mode