GIME MMU Reference
From Super Extended Basic Unravelled
MEMORY MANAGEMENT

The 6809 microprocessor can only address 64K of memory. In order to address more than 64K, a method must be found which will allow the user to switch different blocks of memory into the CPU’s address space. The ability to perform this function is generally referred to as ‘memory management'. There are as many different ways to implement a memory management scheme as there are different computers in the world, and each method will have its own strong points and limitations. In the Color Computer 3, the GIME chip performs the Memory Management Unit (MMU) function.

The GIME chip will allow 512K of RAM to be accessed by the CoCo 3. This 512K address range is called the physical address space. The physical address space is broken down into 64 blocks of 8K each. The six high order bits of any address ($00000-$7FFFF) are the block number. In a 128K machine that means that there will be 16 blocks which will actually have RAM in them, and the other 48 blocks will be treated as three sets of 16 blocks all three of which are mirrors of the high order 16 blocks. A 512K machine will, of course, have 64 blocks of RAM. The GIME chip determines this configuration and there is no known way at this time to trick, fool, or otherwise cajole the chip into allowing you to hang more RAM on the system without adding hardware to the computer. From this pool of 64 8K blocks you may select any eight to fill the CPU’s memory space of 64K. The 64K range, which comprises the address range of the CPU, is referred to as the logical address space. In order to simplify the task of understanding how this is done, it is best for the reader to discard the concept of the fixed memory map of the computer’s memory. From the point of view of the CPU, the Color Computer 3’s RAM is not one large contiguous block from $00000 - $7FFFF. This will undoubtedly cause a certain amount of confusion because the video display section of the Color Computer 3 does consider the RAM as one large contiguous block.

Now, you may ask, if the memory is to be considered as 64 blocks of 8K, how does the CPU know where its memory is. That job is performed by the MMU registers which are located at $FFA0. The eight blocks, which you select as the CPU’s memory, are mapped into the CPU’s address space by the MMU registers as shown in Figure 1.


MMU RegisterCPU Address SpaceLogical block number
$FFA7$E000-$FDFF7
$FFA6$C000-$DFFF6
$FFA5$A000-$BFFF5
$FFA4$8000-$9FFF4
$FFA3$6000-$7FFF3
$FFA2$4000-$5FFF2
$FFA1$2000-$3FFF1
$FFA0$0000-$1FFF0
Figure 1 - Memory Management Unit Registers


It is important to thoroughly understand the concept of memory blocks. The physical address space is composed of 64 physical blocks (they will be referred to simply as blocks). The logical address space is the range of $0-$FFFF which can be addressed by the CPU. The logical address space should be considered as composed of eight 8K blocks of RAM. The MMU registers determine which eight of the 64 blocks from the physical address space will compose the logical address space. As a natural extension, the logical address space may be thought of as being composed of eight logical blocks. The logical blocks are numbered from 0-7 as described in Figure 1 above. The logical blocks are not really actual memory (the physical blocks are actual memory), they are an 8K address space in the address range of the CPU and their position relative to one another may not change in the eyes of the CPU.

The MMU registers have no effect whatsoever on the manner in which the GIME chip displays graphic or text information. For the purpose of graphics, the 512K is considered as one large contiguous super chunk of RAM. In order to make this easier to understand since we are in a "block" frame of mind, just consider the video display memory as 64 contiguous 8K blocks. In other words, the video display memory is just the physical address space and there is no way to move the blocks relative to one another.

The process of setting up the CPUs memory space requires that you select eight blocks, which will comprise the logical address space. Then you must program the MMU registers with the block numbers selected. For example, if you wanted block 56 ($38) to occupy the CPU addresses $0000 - $1FFF (logical block 0), you must store the value $38 into address $FFA0. If you wanted the high 64K of RAM of either a 128K or 512K machine to occupy the logical address space as one contiguous 64K segment, you just load the values $38 - $3F consecutively into the consecutive addresses $FFA0 - $FFA7. This is how Basic sets up the CPU’s memory space.

It is important to realize that there is no prohibition against using the same block in more than one block of the logical address space. If you put the same block number in all of the MMU registers, then the same 8K block of RAM would be mapped into all eight of the logical blocks.

As an example of the power and flexibility which this system of memory management offers, we will consider the logical address space arrangement used by Basic to manipulate super hi-res graphic screens. It is not possible to read data from or write data into the Color Computer 3’s memory unless the memory is in the logical address space. For example, if you wanted to read address $4F859, you would not be able to unless block 39 had been mapped into a logical block by an MMU register. Or, put another way, the value 39 must be in one of the MMU registers ($FFA0 - $FFA7). Basic allocates 32K of memory for its super hi-res graphics screen. In order to manipulate the screen, the 32K screen must be in the logical address space. The bottom 32K of memory in a 128K system ($60000 - $67FFF) is used for the super hi-res screen by Basic. In order to access the screen, this memory is mapped into logical block 1 as shown in Figure 2. Block numbers 48-51 are the super hi-res graphics screen. Block 56 must remain in logical block 0 because it contains all of Basic’s system variables and interrupt vectors, and block 63 must remain in logical block 7 because it contains the Basic program code, which manipulates the super hi-res graphics screen. Block 53 is moved into logical block 6 (overlaying Disk Basic) and is used as the HPUT/HGET buffer.

MMU
Register
Block
Number
Logical
Block Number
Physical
Address
$FFA7637$7E000-$7FFFFProgram
$FFA6536$6A000-$6BFFFHGET Buffer
$FFA5615$7A000-$7BFFFProgram
$FFA4514$66000-$67FFFScreen
$FFA3503$64000-$65FFFScreen
$FFA2492$62000-$63FFFScreen
$FFA1481$60000-$61FFFScreen
$FFA0560$70000-$71FFFSystem DP
Figure 2 - Super Hi-Res Graphics Memory Configuration

There is one final aspect of the Color Computer 3’s memory management system, which must be addressed. The Color Computer 3 has two sets of MMU registers. The first set of eight registers located at $FFA0 should be very familiar to you by now. The second set of eight registers is located at $FFA8 and their function is identical to that of the first set in every aspect. Bit 0 of initialization register 1 ($FF91) is used to determine which one of the sets of registers is determining the makeup of the logical address space. If bit 0 if $FF91 is set to zero, then the eight MMU registers at $FFA0 (task register 0) control the makeup of the logical address space. If bit 0 of $FF91 is set, then the eight MMU registers at $FFA8 (task register 1) control the makeup of the logical address space (see Figure 3). The theory behind the two sets of registers is that each set of registers may be allowed to control a different task by allocating two independent segments of 64K to each task and then simply selecting the desired set of registers in order to enable the desired task. This will work fine but you must be careful to remember that switching between the task registers will do nothing to preserve the status of the CPU registers, nor will it protect you from disasters if you should be interrupted during the transition. Whenever new memory is switched into a logical address space, be sure it isn’t where the program counter, stack, or interrupt service routine is located. Major problems may happen it is:

If the MMU registers have
the data below in them
Then the following blocks
compose the logical address space
$FF91
bit0=0
$FF91
bit0=1
$FFA024$FFA834 $00002434
$FFA126$FFA956 $20002656
$FFA215$FFAA43 $40001543
$FFA356$FFAB34 $60005634
$FFA441$FFAC35 $80004135
$FFAS42$FFAD08 $A0004208
$FFA662$FFAE36 $C0006236
$FFA761$FFAF00 $E0006100
Figure 3 - MMU task registers

Special notes:

1) All of the MMU registers may be read from as well as written to. However, only the lower 6 bits of data are accurate. The top two bits should be masked off after they are read. Also, in order to enable the MMU registers, bit 6 of $FF90 must be set.

2) The CoCo enable bit (bit 7, $FF90) does not have any effect upon the operation of the MMU registers. The MMU enable bit (bit 6, $FF90) must be set in order for the MMU registers to be operable.

3) The area from $FF00 - $FFFF is used for system input/output and is never affected by the MMU registers. The area from $FE00 - $FEFF is a special page (256 bytes) of RAM and may be affected by the MMU registers if MC3 (bit 3, $FF90) is clear.